1. Field of the Invention
The present invention relates to a bypass scan path for serially transmitting various data and an integrated circuit device using the same.
2. Description of the Background Art
In integrated circuit devices, especially in ones having complex functional logics inside, it is extremely difficult to test internal conditions using only primary input/output terminals. Such difficulty is expressed by two terms "observability" and "controllability".
The controllability indicates difficulty in controlling signals inside a circuit. The observability indicates difficulty in observing internal conditions in a circuit.
For example, in order to know if a failure exists at a certain point inside a circuit, it is necessary to be able to freely control an input signal applied thereto. Also, an output obtained by predetermined input must be precisely observed. Accordingly, if one of the observability and controllability is lacking, it is impossible to make a determination as to whether there exists a failure inside the circuit. However, in an integrated circuit device having complex functional logics, a large number of gates are interposed between a tested portion and a primary input terminal. Accordingly, it is extremely difficult to obtain excellent observability and controllability. Furthermore, with development in the semiconductor technique, integrated circuit devices are increasingly becoming larger scale and more complex to make testing inside circuits extremely difficult.
Accordingly, the significance of so-called designing for facilitating testing has been on the increase. Application of testing includes a plurality of steps, i.e., the steps of producing test data, execution of operation of a circuit to be tested with the test data, output of test result, and confirmation thereof. With development of larger scale circuits, a time required for testing increases and it is becoming more and more significant to complete testing in a short time.
Accordingly, to facilitate testing, a method referred to as scan designing described below is often used. In the scan designing, shift register latches (hereinafter referred to as SRL) are first provided at an observation point (a position at which output is to be observed) and a control point (a position at which input is to be set) inside an integrated circuit. A plurality of SRLs are connected in series to form a shift path (scan path) where data can be transmitted.
Test data is externally applied to a scan path and transmitted serially in the scan path and desired test data is set in a SRL at a control point. Stored data at each SRL is applied to a circuit to be tested. An output of the circuit to be tested (test result data) is outputted to a SRL at each observation point and stored therein. The stored data of the SRL is again serially transmitted on the scan path and outputted as a serial signal outside from an output terminal. Provision of such a scan path enables observability and controllability in a deep portion of an integrated circuit device.
However, the scan designing handles data with time. Accordingly, when a bit length of a scan path increases because of an improvement in large scale integrated circuit devices, a transmission time of data becomes longer accordingly and a testing time also increases. In testing of integrated circuits, reduction of test time and the number of test pins are serious problems to be achieved.
Conventionally, accordingly, a single scan path is divided into a plurality of portions and a bypass path is provided for directly connecting an input and an output bypassing the scan path in each portion to selectively transmitting inputted data to either of SRLs and a bypass path. Thus, since required portion only performs operation of shifting data in a scan path, data transmission time is reduced to reduce test time.
A conventional example of a scan path having bypass means (hereinafter referred to as a bypass scan path) will be described below.
FIG. 13 is a block diagram illustrating configuration of a conventional bypass scan path disclosed in IEICE Technical Report, CAS90-97, VLD9-75, ICD90-146 "An Enhancement of Cell-Based Test Design Method for Boundary Scan Architecture" by Hashizume et al., for example. In the figure, the bypass scan path includes a scan path 10 and a scan path selecting circuit 20. Scan path 10 includes a plurality of SRLs 11-16 connected in series. Scan path selecting circuit 20 includes 2-input and 1-output multiplexer 21, selection data holding latch 22 and an AND gate 23. A serial signal inputted into scan path selecting circuit 20 from a serial input terminal (hereinafter referred to as a SI terminal) 201 is applied to one input terminal of multiplexer 21 and also applied to a SRL 11 at the first stage of scan path 10 through a serial output terminal (hereinafter referred to as a SO terminal) 202. An output of a SRL 16 at the final stage of scan path 10 is applied to the other input terminal of multiplexer 21 and a data input terminal D of selection data holding latch 22 through an SI terminal 203. A mode latch signal is applied from input terminal 205 to a clock signal input terminal C of selection data holding latch 22. A signal outputted from an output terminal Q of selection data holding latch 22 is applied to a control terminal of multiplexer 21 as a select control signal of multiplexer 21 and also applied to one input terminal of AND gate 23 after its logic is inverted. A group of control signals for controlling operation of scan path 10 are applied from an input terminal 207 to the other input terminal of AND gate 23. The group of control signals include a strobe signal STB, an update signal UD, shift clock signals SCLK1 and SCLK2. AND gate 23 is individually provided for each of strobe signal STB, update signal UD, shift clock signals SCLK1 and SCLK2, which input-controls the group of control signals. An output of AND gate 23 is applied to each SRL through an output terminal 208.
Data input terminals DI1-DI6, data output terminals DO1-DO6 are connected to each of SRLs 11-16, respectively. Data input terminals DI1-DI6 are connected to input terminals, i.e. observation points of a circuit to be tested inside an integrated circuit device. Data output terminals DO1-DO6 are connected to output terminals, i.e., control points of a circuit to be tested inside the integrated circuit device. In a test mode, each of SRLs 11-16 applies held test data to each control point through each of data output terminals DO1-DO6. Each of SRLs 11-16 also captures test result data obtained from each observation point from each of data input terminals DI1-DI6. On the other hand, in a normal mode, each of SRLs 11-16 attains a transmissive state (a data through state), where system data is transmitted between data input terminals DI1-DI6 and data output terminals DO1-DO6.
FIG. 14 is a block diagram illustrating one example of a configuration of a SRL shown in FIG. 13. In the figure, the SRL includes 2-input data latch 31, and data latches 32 and 33. Test result data or system data is applied to a first data input terminal D1 of 2-input data latch 31 through a data input terminal DI (any one of input terminals DI1-DI6 in FIG. 13). Serial signals (select data, test data, test result data) are applied to a second data input terminal D2 of 2-input data latch 31 through a SI terminal 34. A strobe signal STB is applied to a first clock signal input terminal C1 of 2-input data latch 31 through an input terminal 35. A shift clock signal SCLK1 is applied to a second clock input terminal C2 of 2-input data latch 31 through an input terminal 36. 2-input data latch 31 captures and holds data from data input terminal D1 when a strobe signal STB is at a H level, and captures and holds serial data from SI terminal 34 when a shift clock signal SCLK1 is at a H level. A signal outputted from an output terminal Q of 2-input data latch 31 is applied to each input terminal D of data latches 32 and 33. An update signal UD is applied to a clock signal input terminal C of data latch 32 through input terminal 37. A shift clock signal SCLK 2 is applied through input terminal 38 to a clock signal input terminal C of data latch 33. Data latch 32 captures and holds an output signal of 2-input data latch 31 when an update signal UD is at a H level. Data latch 33 captures and holds an output signal of 2-input data latch 31 when shift clock signal SCLK2 is at a H level. A signal outputted from an output terminal Q of data latch 32 is applied to a data output terminal DO (any one of data output terminals DO1-DO6 in FIG. 13). A signal outputted from an output terminal Q of data latch 33 is applied to an SO terminal 39. SI terminal 34 is connected to SO terminal 39 of a SRL at a previous stage or SO terminal 202 in FIG. 13. SO terminal 39 is connected to SI terminal 34 of a SRL at a following stage or SI terminal 203 in FIG. 13. Input terminals 35-38 are connected to output terminal 208 in FIG. 13.
The SRL shown in FIG. 14 shifts a serial signal inputted from SI terminal 34 to SO terminal 39 in response to non-overlapping 2-phase shift clock signals SCLK1, SCLK2. Data inputted from data input terminal DI is captured in 2-input data latch 31 in response to a strobe signal STB. Held data of 2-input data latch 31 is captured in data latch 32 in response to an update signal UD and outputted from data output terminal DO.
For the reference, an example of a circuit configuration of the SRL shown in FIG. 14 is illustrated in FIG. 15. As shown in the figure, 2-input data latch 31 is formed of inverters IV1-IV4 and N channel MOS transistors TR1 and TR2, data latch 32 is formed of inverters IV5-IV7 and an N channel MOS transistor TR3 and data latch 33 is formed of inverters IV8-IV10 and an N channel MOS transistor TR4. Inverters IV3 and IV4, inverters IV5 and IV6, and inverters IV8 and IV9 form ratio type latch circuits, respectively.
FIG. 16 is a circuit diagram illustrating one example of a structure of the selection data holding latch shown in FIG. 13. In the figure, selection data holding latch 22 includes inverters IV11-IV13 and N channel MOS transistors TR5 and TR6. Inverters IV11 and IV12 are connected in antiparallel to form a ratio type latch circuit. A transistor TR5 is interposed between an input terminal of inverter IV11 and data input terminal D. A gate of transistor TR5 is connected to clock signal input terminal C. An input terminal of inverter IV11 is grounded through transistor TR6. A gate of transistor TR6 is connected to a reset terminal R. Inverter IV13 is interposed between an output terminal of inverter IV11 and an output terminal Q.
FIG. 17 is block diagram illustrating configuration of a test module in which a test aids circuit by a scan path shown in FIG. 13 is incorporated. In the figure, each of SRLs 11-16 is connected to an input terminal or an output terminal which is a control point or an observation point of a functional module (hereinafter referred to as BUT) of an objective of testing to form scan path 10. In the example of FIG. 17, SRLs 11-13 are connected to input terminals of BUT 40 and SRLs 14-16 are connected to output terminals of BUT 40. BUT 40 includes a predetermined logic circuit inside. Scan path 10 is connected to scan path selecting circuit 20. A test aids circuit is formed of scan path 10 and scan path select circuit 20, and the test aids circuit and BUT 40 form a test module 50. A serial signal is inputted from a SI terminal 501 of test module 50 and a serial signal is outputted from a SO terminal 504. SI terminal 501, SO terminal 504 are respectively connected to a SI terminal 201 and a SO terminal 204 of scan path selecting circuit 20. A mode latch signal, a reset signal and a group of control signals are respectively inputted into input terminals 205, 206, 207 of scan path selecting circuit 20 from input terminals 505, 506, 507.
FIG. 18 is a block diagram illustrating one example of a structure of an integrated circuit device in which the test module shown in FIG. 17 is incorporated. In the figure, inside integrated circuit device 60, three test modules 50a-50c are provided, for example. Structure of each test module 50a-50c is similar to that of test module 50 in FIG. 17. Each of test modules 50a-50c is serially connected between a SI terminal 601 and a SO terminal 602 related to select data and test data. That is, SI terminal 601 is connected to a SI terminal 501 of test module 50a, a SO terminal 504 of test module 50a is connected to a SI terminal 501 of test 50b, a SO terminal 504 of test module 50b is connected to a SI terminal 501 of test module 50c and a SO terminal 504 of test module 50c is connected to a SO terminal 602. Thus, a single scan data transmitting path is formed between SI terminal 601 and SO terminal 602. The group of control signals inputted from input terminal 603 are applied to each input terminal 507 of each test module 50a-50c. A reset signal inputted from input terminal 604 is applied to each input terminal 506 of each of test modules 50a-50c. A mode latch signal inputted from input terminal 605 is applied to each input terminal 505 of each of test modules 50a-50c. System data inputted from input terminals 606-608 are applied to test module 50a and processed. The system data processed by test module 50a is applied to test module 50b and processed. Also, a part of system data processed by test module 50a is applied to test module 50c and processed. System data inputted from input terminals 609, 610 are applied to test module 50c and processed. The system data processed by test module 50b is outputted from output terminals 611-613 to outside. The system data processed by test module 50c is outputted from output terminals 614-616 to outside.
Next, operation of the integrated circuit device shown in FIG. 18 will be described according to the following items.
(1) Operation in a normal mode PA1 (2) Operation in a test mode PA1 &lt;1&gt; Reset PA1 &lt;2&gt; Transmission of selection data PA1 &lt;3&gt; Transmission of test data PA1 (a) Shift-In of Selection Data PA1 b) Capturing of Selection Data PA1 a) Shift-In of Test Data PA1 b) Provision of Test Data PA1 c) Capturing of Test Result Data PA1 d) Shift-Out of Test Result Data
a) Shift-in of selection data PA2 b) Capturing of selection data PA2 a) Shift-in of test data PA2 b) Provision of test data PA2 c) Capturing of test result data PA2 d) Shift-out of test result data
Here, the normal mode refers to a mode in which inputted system data is processed and outputted.
Reset in a test mode is made in order to select a scan path (shift path) in each test module 50a-50c as preparation for transmitting selection data. The selection data is data for making a determination as to whether a scan path is to be selected or a bypass path is selected as a transmission path of data in each test module.
(1) Operation in Normal Mode
A reset signal is raised to an active level, that is, a H level, and selection data holding latch 22 in scan path selecting circuit 20 is reset. Thus, an output signal of output terminal Q in a selection data holding latch 22 is brought to a L level and one input terminal of AND gate 23 is fixed to a H level. As a result, AND gate 23 transmits a group of control signals to each of SRLs 11-16. At this time, a strobe signal STB and an update signal UD are fixed at H level and shift clock signals SCLK1 and SCLK2 are fixed to a L level. As a result, in the SRL shown in FIG. 14, 2-input data latch 31, data latch 32 merely operate as a non-inversion drivers. Accordingly a transmissive state (data through state) is implemented between data input terminal DI and data output terminal DO. From input terminals 606-601, system data is inputted. The inputted system data is processed by BUT 40 in each test module 50a-50c and then externally outputted from output terminals 611-616. At this time, in a SRL in each scan path, a transmissive state is implemented between data input terminal DI and data output terminal DO, so that transmission of system data is not prevented.
(2) Operation in Test Mode
&lt;1&gt; Reset
A reset signal is raised to an active level, for example a H level. Thus, selection data holding latch 22 in scan path selecting circuit 20 is reset. As a result, an output signal of output terminal Q in selection data holding latch 22 is fixed to a L level. Multiplexer 21, which is supplied with a selection control signal of a L level from selection data holding latch 22, selects an output signal of scan path 10, that is, an input signal from SI terminal 203 and outputs it to SO terminal 204. On the other hand, since one input terminal of AND gate 23 is fixed to a H level, AND gate 23 transmits a group of control signals to each of SRLs 11-16. Accordingly, scan path 10 comes in a data transmittable state. Operation described above is similarly performed in each of test modules 50a-50c. Accordingly, in each of test modules 50a-50c, a shift path, i.e. scan path 10 is selected as a data transmission path.
&lt;2&gt; Transmission of Selection Data
Selection data is serially inputted from SI terminal 601. At this time, shift clock signals SCLK1 and SCLK2 are provided as non-overlapping two-phase clock signals. Accordingly, each SRL in scan path 10 shifts selection data inputted from SI terminal 34 by alternate latch operations of 2-input data latch 31 and data latch 33. Here, selection data is inputted together with dummy data. Selection data is finally set in a SRL at the final stage in a scan path in each of test modules 50a-50c. Dummy data is set in other SRLs. For example in a scan path 10 having structure as shown in FIG. 13, selection data is set in SRL 16 and dummy data are set in other SRLs 11-15. Selection data for selecting a scan path is determined to "0". Selection data for selecting a bypass path is determined to "1". Accordingly, when selecting a scan path, data of "XXXXX0" is set in each of SRLs 11-16. When selecting a bypass path, data of "XXXXX1" is set in each of SRLs 11- 16. Here, "X" is dummy data. When the selection data reaches the SRL 16 at the final stage in scan path 10 in each of test modules 50a-50c, input of selection data and shift operation of SRL are stopped.
A mode latch signal is raised to an active level, i.e., a H level. Thus, selection data holding latch 22 inside scan path selecting circuit 20 captures and latches data held by SRL 16, that is, selection data. When selection data holding latch 22 latches selection data "0", an output signal of selection data holding latch 22 attains a "L" level, so that multiplexer 21 selects an output signal of scan path 10. Also, AND gate 23 transmits a group of control signals to each of SRLs 11-16, so that scan path 10 comes in a data transmittable state. When selection data holding latch 22 latches selection data "1", an output signal of selection data holding latch 22 attains a H level, so that multiplexer 21 selects an input signal from SI terminal 201. Also, since one input terminal of AND gate 23 is fixed to a H level, it does not transmit a group of control signals to each of SRLs 11-16. Accordingly, scan path 10 comes in a data untransmittable state.
&lt;3&gt; Transmission of Test Data
Test data is serially inputted from SI terminal 601. At this time, shift clock signals SCLK1 and SCLK2 are provided as non-overlapping two-phase clocks signals. Accordingly, in a test module in which a scan path is selected by MUX 21, each of SRLs 11-16 sequentially shifts test data inputted from SI terminal 34 to SO terminal 39. On the other hand, in a test module in which a bypass path is selected by MUX 21, the test data inputted from SI terminal 201 is directly outputted to SO terminal 204 from multiplexer 21 bypassing scan path 10. Accordingly, the bit length in a transmission path of test data is reduced to the number of stages of required SRLs to reduce the number of testing of test data. It shortens time of setting test data. Upon arrival of test data at each SRL in a given scan path 10, input of test data and shifting operation of SRL are stopped.
An update signal is raised to a H level, and test data held in 2-input data latch 31 of a SRL is captured and held by data latch 32. The test data held in 2-input data latch 32 is provided to an input terminal of a corresponding BUT 40 through data output terminal DO. A BUT 40 provided with the test data processes the test data according to its internal logic structure and outputs test result data to its output terminal.
A strobe signal STB is raised to a H level. Thus, in a SRL connected to an output terminal of BUT 40, test result data provided through data input terminal DI is captured and held by 2-input data latch 31.
Shift clock signals SCLK1 and SCLK2 are provided as non-overlapping two-phase clocks signals. As a result, the test result data held by 2-input data latch 31 of a SRL is shifted through data latch 33 and outputted to SO terminal 39. At this time, selection data holding latch 22 is holding selection data, so that in a test module in which a bypass path is selected, scan path 10 does not perform shift operation, where a bypassing path of data is formed. Accordingly, also in shift-out of test result data, similarly to the above-described shift-in of test data, a required scan path 10 only performs shifting operation to reduce a bit length of a data transmission path. Accordingly, the shift-out time of test result data is reduced. The shifted test result data is externally outputted from SO terminal 602.
Above-described test operations are repeatedly executed changing patterns of test data. Also, the testing is executed about all the test modules 50a-50c.
Analyzing and verifying the test result data outputted from SO terminal 602 outside thereof, presence and absence of abnormality inside integrated circuit device 60 can be diagnosed.
Now, IEEE (The Institute of Electrical and Electronics Engineers, Inc.) defines various standards for standardization of test design using a boundary scan. The standards are described in detail in IEEE Std. 1149. 1-1990; published by the Institute of Electrical and Electronics Engineering, inc., 345 East 47th street, New York, N.Y. 10017, USA. May 21, 1990. In the standards, sorts and number of signals used for testing, circuit configuration inside an integrated circuit device, and the like are clearly defined.
FIG. 19 is a block diagram illustrating structure of an integrated circuit device in which the test module shown in FIG. 17 and a test controller required for the boundary scan test defined in the standard of IEEE 1149.1 are incorporated. In the figure, a test controller 70 is connected to a TCK terminal 621, a TMS terminal 622, a TDI terminal 623, a TRST terminal 624 and a TDO terminal 625. A test clock signal is inputted from TCK terminal 621. A test mode signal is inputted from TMS terminal 622. A test reset signal is inputted from TRST terminal 624. Test controller 70 generates a group of control signals and a reset signal on the basis of these test clock signal, test mode signal and test reset signal. The group of control signals and the reset signal are applied to each of test modules 50a-50c. Selection data and test data are inputted from TDI terminal 623, which passes test controller 70 and are applied to SI terminal 501 of test module 50a from SO terminal 701. The test result data obtained from SO terminal 504 of test module 50c is externally outputted from TDO terminal 625 after passing through test controller 70. A mode latch signal supplied to test modules 50a-50c can not be generated by test controller 70, so that it must be directly inputted from outside through an input terminal 605. This is because the boundary scan test defined by the IEEE 1149.1 did not anticipate appearance of a scan path having a bypass path.
In the standard of IEEE 1149.1, sorts of pins provided in an LSI chip for testing are limited to five sorts, TCK terminal 621, TMS terminal 622, TDI terminal 623, TRST terminal 624 and TDO terminal 625. Accordingly, the integrated circuit device 61 in FIG. 19 having input terminal 605 for a mode latch signal has a structure which does not meet with the standard of IEEE 1149.1.
The operation of integrated circuit device 61 shown in FIG. 19 is substantially the same as operation of the integrated circuit device 60 shown in FIG. 18, so that the description thereof is not repeated.
A conventional bypass scan path configured as described above has a large number of signals for controlling a bypass scan path. Accordingly, it had a problem of an increase of the number of terminals of an LSI chip and an increase of the number of interconnections inside. Also, when using a conventional bypass scan path as an internal test aids circuit for an integrated circuit device introducing an IEEE 1149.1 boundary scan which is a board level standard test method, a terminal 605 for inputting a mode latch signal has to be separately provided in an LSI chip, so that there existed a problem that the integrated circuit device does not meet with the standard of the IEEE 1149.1. As the result, it had disadvantages that commercially available CAD tools (test pattern producing software for boundary scan and the like) can not be used and that board test according to the standard (a method of packaging a plurality of LSI chips on a board and testing the plurality of LSI chips simultaneously) can not be performed, either.